Summary
Proteus Virtual System Modelling (VSM) combines mixed mode SPICE circuit simulation, animated components and microprocessor models to facilitate co-simulation of complete microcontroller based designs.
The ‘Proteus VSM for ARM® Cortex™-M3’ product includes the following main software modules:
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Variants
The following is a current list of supported variants in the ARM® Cortex™-M3 family:
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Features
We believe our simulation models are the most accurate and the most complete on the market today. A summary of model capabilities is listed below:
- Fully simulates the entire instruction set (excluding operations for multiprocessor support).
- Supports all port and other I/O pin operations.
- Supports sleep and deep sleep modes.
- Supports Watchdog Timer.
- Supports General Purpose Timers in all modes.
- Supports Universal Asynchronous Receiver/Transmitter (UART) with FIFO mode.
- Supports Synchronous Serial Interface (SSI) with following frame types: Freescale, MICROWIRE, or Texas Instruments.
- Supports Inter-Integrated Circuit (I2C) in all modes on appropriate devices.
- Supports Analog Comparators in all configurations of signal sources.
- Supports Analog-to-digital 10-bit converter (ADC) with several input channels plus internal temperature sensor.
- Supports internal code and data FLASH memory including Cortex-M3 memory region protection.
- Supports all interrupt modes.
- Internally generated processor clock for performance. Event timing accurate to one clock period.
- Provides internal consistency checks on code (e.g. execution of invalid op-codes, illegal memory accesses, stack integrity checking, etc.).
- Fully integrated in to the VSM source level debugging system.
- Fully integrated into the Proteus Diagnostic Control System.
Limitations
The following is a listing of known limitations in the current version of the ARM® Cortex™-M3:
- Bitband alias regions are of type XN (Execute Never).
- Cache information is not used.
- Systick calibration value register (SYST_CALIB) is ignored.
- Data Barrier instructions (DMB,DSB) are treated as NOP.
- Register PLLCFG is not modelled.
- Clock Verification Timers and Internal brown-out detector not modelled.
- Registers DR2R,DR4R,DR8R,SLR are not modelled.
- Loopback feature of the I2C Module is not documented and therefore not modelled.
Compilers
Supported Third Party Compilers
Proteus VSM models will fundamentally work with the exact same HEX file as you would program the physical device with. However, far more debugging information is available when using a compiler to write the firmware and providing these object files to Proteus in place of the HEX file provides a much richer working environment.
We recommend you use the free Labcenter VSM Studio IDE. This will greatly simplify the task as it will automatically configure supported compilers to work with a Proteus VSM simulation.
If you prefer to work inside your own IDE then you will need to set your compiler options manually. After compiling for debug, all you need to do is specify the debug file from the compiler as the program property of the microcontroller on the schematic.
VSM Studio supported toolchains
- IAR
- GCC
- KEIL