Proteus VSM for PICCOLO®

Summary

Proteus Virtual System Modelling (VSM) combines mixed mode SPICE circuit simulation, animated components and microprocessor models to facilitate co-simulation of complete microcontroller based designs.
The ‘Proteus VSM for PICCOLO®’ product includes the following main software modules:

Variants

The following is a current list of supported variants in the PICCOLO® family:

Features

We believe our simulation models are the most accurate and the most complete on the market today. A summary of model capabilities is listed below:

• Fully simulates the entire instruction set.
• Supports all port and other I/O pin operations.
• Supports all timers including watchdog timer.
• Supports both Enhanced and High-Resolution Pulse Width Modulator (EPWM and HRPWM) modules in all modes.
• Supports communication interfaces: I2C, SCI and SPI modules.
• Supports Analogue-to-Digital Conversion (ADC) module including support for voltage reference pins and internal temperature sensor.
• Supports Enhanced Capture (ECAP) module.
• Supports Analogue Comparator modules including support for internal and external voltage references.
• Supports all interrupt and power-safe modes.
• Internally generated processor clock for performance. Event timing accurate to one clock period.
• Provides internal consistency checks on code (e.g. execution of invalid op-codes and illegal memory accesses)
• Fully integrated in to the VSM source level debugging system.
• Fully integrated into the Proteus Diagnostic Control System.

Limitations

The following is a listing of known limitations in the current version of the PICCOLO®:

• The Device_cal() routine is programmed into TI reserved memory by the factory. It is used to calibrate the internal oscillators and ADC with device specific calibration data. In the model the procedure contains a single instruction – Return from Routine
• The nominal frequency of both INTOSC1 and INTOSC2 is 10 MHz. Two 16-bit registers are provided for trimming each oscillator at manufacturing time (called coarse trim) and also provide you with a way to trim the oscillator using software (called fine trim).This is not implemented in the model.
• It is possible for the clock source (internal or external) of the DSP to fail. When the PLL is not disabled, the main oscillator fail logic allows the device to detect this condition. This behaviour is not implemented in the model.
• There are two CPU-Timer emulation modes in the hardware device.CPU-Timer Emulation Modes: These bits are special emulation bits that determine the state of the timer when a breakpoint is encountered in the high-level language debugger. These bits are not modelled.
• SPI Emulation mode is not modelled. This means that SPIPRI register behaviour is not implemented and that SPIRXEMU Register is not used (SPIRXBUF is used for normal operation and fully supported in the model)
• Digital loopback bit (I2CMDR.DLB) of the I2C model and the ECAP Emulation control bits are not supported by the model. All other I2C modes are fully modelled.
• MEP calibration logic (MRPWR.MEPOFF) is initially disabled in the hrPWM module.
• Code Security is not implemented.

Compilers

Proteus VSM models will fundamentally work with the exact same HEX file as you would program the physical device with. However, far more debugging information is available when using a compiler to write the firmware and providing these object files to Proteus in place of the HEX file provides a much richer working environment.

We recommend you use the free Labcenter VSM Studio IDE. This will greatly simplify the task as it will automatically configure supported compilers to work with a Proteus VSM simulation.

If you prefer to work inside your own IDE then you will need to set your compiler options manually. After compiling for debug, all you need to do is specify the debug file from the compiler as the program property of the microcontroller on the schematic.

VSM Studio supported toolchains Code Composer