Pico SDR 2nd Generation

Key Features:

Prototyping is easier than ever with this new 4×4 MIMO SDR platform, with 4 channels perfectly synchronized on one FPGA. Use Simulink to leverage the power of a large Virtex FPGA without writing a single line of HDL code. 70 MHz to 6 GHz on one single radio: Unlock the full performance of the AD9361 across all frequency bands.

•  4×4 in one single FPGA perfectly synchronized
• Fully integrated with Matlab Simulink and Xilinx System Generator (model-based design tools)
• AD9361 Radio Frequency Integrated Circuit (RFIC)
• Software defined up to 6 GHz and 56 MHz BW
• GNU Radio Support
• Small form factor: 215 mm x 48 mm x 290 mm
• Embedded Linux PC: connect remotely from any computer or run standalone
• Plug-and-play, with Ethernet, PCI Express and VITA-49 Radio Transport Protocol (VRT)
• Low Latency (75 µs roundtrip) and high speed (10 Gbps) PCIe interface
• QAM64 OFDM Ref Design*

70 MHz to 6 GHz on one single radio

The PicoSDR 4×4 relies on one single 70 MHz – 6 Ghz radio card, built on the agile and high-performance AD9361 Radio Frequency Integrated Circuit (RFIC), that offers the full performance on all bands frequency.

• RF 2×2 transceiver with integrated 12-DACs and ADCs
• 70 MHz to 6 GHz frequency range with integrated fractional-N synthesizers (2.4 Hz maximum LO step size)
• Supports TDD and FDD operation
• Tunable channel bandwidth: 200 kHz to 56 MHz
• Receiver sensitivity with a typical noise figure of 7 dB from 200MHz to 4 GHz and 10dB from 70MHz to 6 GHz
• 100dB RX gain control with real-time monitor and control signals for manual gain
• Independent automatic gain control
• TX OP1dB : +18dBm from 200-4000MHz and +10dBm from 200-6000MHz

• Highly linear broadband transmitter (TM3.2 20MHz-16QAM LTE signal):
  • ACPR < -50dB for +10dBm and <-45dB for 0 dBm at 2.4GHz and 6GHz respectively
  • EVM = 2.5% and 3% for +10dBm and <-45dB for 0 dBm at 2.4GHz and 6GHz respectively
• TX noise: =-150 dBm/Hz noise floor
• 100dB+ TX gain control with 31dB external gain control

Key Features:

Phased-array, beam forming, direction finding and MU-MIMO is now affordable with this new 8×8 MIMO SDR, offering 8 TRx channels per FPGA. With the ability to connect two units for perfectly synchronized 16×16, automatic gain & phase calibration, dedicated links to bring all IQ streams into one master FPGA, building large MIMO systems has never been easier.

• 8×8 on one single FPGA
• Easy to connect two units for perfectly synchronized 16×16 or more
• Dedicated low-latency point-to-point links bring all IQ streams into one master FPGA (16×16 or more)
• Automatic gain and phase calibration for phased-array, beam forming, direction finding and MU-MIMO
• Fully integrated with Matlab Simulink and Xilinx System Generator (model-based design tools)
• AD9361 Radio Frequency Integrated Circuit (RFIC)
• Software defined up to 6 GHz and 56 MHz BW
• Small form factor: 385 mm  x 360 mm x 45 mm
• Embedded Linux PC: connect remotely from any computer or run standalone

• Plug-and-play, with Ethernet, PCI Express and VITA-49 Radio Transport Protocol (VRT)
• Low Latency (75 µs roundtrip) and high speed (10 Gbps) PCIe interface
• QAM64 OFDM Ref Design*

8×8 on one single FPGA

Click on the image to enlarge it

Automatic gain & phase calibration for phased-array, beam forming, direction finding and MU-MIMO

Here’s a demonstration of our calibration feature on the TitanMIMO-6, another of Nutaq’s product.